The present invention relates to a logic state transition detector circuit for CMOS devices, and specifically, to detector circuits for detecting address changes in asynchronous CMOS RAM devices for providing timing signals to the internal logic in the memory device.
The sequence of operation for access of an asynchronous RAM begins with address transition detection. The address transition detectors of the prior art typically utilize static pulse generators incorporating an odd number of inverters coupled to NAND or NOR gates for generating an output pulse. The use of NAND or NOR gates, however, require a minimum number of devices to implement the logic at the expense of speed and chip surface area.
It is therefore, an object of the present invention to provide an address transition detector requiring a low number of devices.
It is another object of the present invention to provide an address transition detector requiring less space and having greater speed.
These and other objects of the present invention are obtained by providing an address transition detector (ATD) requiring only 20 devices to implement the necessary logic. The ATD includes two pairs of serially connected P-channel devices connected between a power supply and a common first node. The first pair of transistors detect a positive transition of an address change while the second pair of transistors detect a negative transition of an address change. When detecting a transition, the respective pair of transistors will deposit a charge on the common first node. An inverter is also coupled to the common first node such that its output provides a low output pulse when the common node is charged to a high logic level. However, an additional inverter may be provided at the output such that the output provides a high output pulse in response to an address change if desired.
Also included in the invention is a latching transistor which holds the common first node to a high logic level after being charged to a high state. The node will remain at this level until a reset signal is provided by a delay circuit comprising an odd number of inverters, typically three in number, coupled between the output of the inverter and the gate of an N-channel transistor. The N-channel transistor provides a reset signal to the common node based on the delayed output signal.
By utilizing the combination of this feedback delay with the pairs of P-channel detector transistors, neither NOR or NAND gate are required in the detection circuitry, and thus, a lesser number of devices are required. As a result, less space is required to implement the detector circuit, which may also enhance the speed of the device.